About the Project
This work will research, design and develop an Energy Harvesting Image sensor which has integrated image processing and analysis functions to produce a fully self-powered autonomous sensor system capable of object detection, presence detection, motion detection, user identification etc.
Energy Harvesting sensors are extremely power limited, typically 10nW-100nW is available and so power saving techniques are critical. Transmitting the image off-chip is often the most energy consuming operation, so on-chip image processing is an effective way to reduce the data rate and power budget.
It is hoped that this will produce a demonstrator device, fabricated in an existing cutting-edge process technology showing self-powered motion detection. This project will determine what size (cost) of sensor is required, what illumination levels are necessary to sustain self-powered operation and what types of processing can be implemented inside this power constraint.
Energy Harvesting and “Always On Imaging” is an emerging technology, enabled by recent advances in process technologies (DTI, 3D-stacking, FD-SOI etc.). Traditional imagers and their system architectures are far too power hungry for this application. Merely reducing the power consumption of circuit elements is insufficient – new imager architectures are required to reduce capacitance, save power and lower bandwidth in order to enable self-powered operation.
The student will use ST/UoE existing EH imager platform to perform a feasibility study to develop and validate a model of real-world scenes, power generation and image data. The next phase will be to research/design algorithms suitable for ultra low power implementation and then extend/re-design imager architecture to implement this on a system-on-chip. After this is fabricated, the device will be evaluated to measure imager performance and object recognition capabilities.
The first phase of this project will be to develop a high-level model of the system to determine power generation under typical operation and the typical images that are produced by the existing EH imager device. The second phase will be to research and CMOS circuit design of candidate harvesting & imaging readout circuits into a device capable of demonstrating self-powered object detection. After fabrication, the student will then debug and validate the device.
The student is expected to carry out high quality research, present work at international conferences and publish in high quality peer-reviewed research journals.
The student will have a desk at both the University and in ST Edinburgh office and has the option to work at either location depending on the specific work. Working from home or on flexible hours is also an option. The student will work within ST (or remotely) when progressing & working on circuit designs; the student shall be at the university labs for measurements, characterisation, training opportunities, etc.
The student will be based at the Scottish Microelectronics Centre (SMC) (https://www.smc.eng.ed.ac.uk/home) with state-of-the-art nano-fabrication and semiconductor post-processing facilities. The SMC is home to many research groups in semiconductors & engineering which offers a vibrant environment for mutual exchange of ideas and collaboration.
STMicroelectronics (R&D) Ltd & the University of Edinburgh are equal opportunities employers. We are open to discussing flexible options for this role including, but not limited to: flexible working hours; working from home & part time research degree/part time working. https://www.st.com/content/st_com/en/about/careers/we-develop-talents.html
CDT Essential Criteria
A Masters level degree (MEng, MPhys, MSc) at 2.1 or equivalent in Electronic & Electrical Engineering, Physics or Computer Science. BEng 1st class considered.
CMOS transistor operation knowledge.
Circuit design experience and/or understanding.
Desire to work collegiately, be involved in outreach, undertake taught and professional skills study.
English (written & spoken) proficiency.
CMOS design experience in academic (taught or research), private research or industrial settings.
Use of the Cadence design suite or similar.
FPGA understanding or FPGA development experience.
Image processing/signal processing, theory and implementation
The CDT in Applied Photonics provides a supportive, collaborative environment which values inclusivity and is committed to creating and sustaining a positive and supportive environment for all our applicants, students, and staff. For further information, please see our ED&I statement https://bit.ly/3gXrcwg. Forming a supportive cohort is an important part of the programme and our students take part in various professional skills workshops, including Responsible Research and Innovation workshops and attend Outreach Training.